The present invention pertains in general to a multiple processor system and, more particularly, to the intercommunication network between separate processors in the multiple processor system.
In order to increase the processing capability of any system, multiple processor arrays have been utilized. Typically, these multiple processor arrays are comprised of independent central processing units (CPUs) which are disposed.in an array with each having a local bus with local peripheral units disposed thereabout. The local buses of each of the CPUs is then interfaced with a global bus. In turn, the global bus is interfaced with a system bus. One type of system bus is a VME bus.
When handling data flow between the system bus and each of the CPUs in the array of processors, traffic must be routed over the global bus. In order for information to be transmitted: either from the processors to the system bus or from the system bus to the processors, there must be some type of arbitration. Typically, a bus request is sent out to the global bus control system and then the bus request granted to that requesting device. Data can then be transmitted over the bus in the appropriate manner. This is a conventional operation. However, the global bus becomes the limiting factor in transfer of data between processors and the system bus, and even between adjacent processors on the global bus. This is due to the fact that only one device can occupy the global bus at a given time.
One type of CPU that has been used widely is a Digital Signal Processor (DSP). These processors execute instructions at a very high rate but, unfortunately, like most processors, the architecture of the processor will determine the limitations of that processor with respect to communicating with the global bus, communicating with other processors and handling interrupts. Typically, most DSPs are designed for single chip use and must be provided with another layer of infrastructure in order to be incorporated into an array of microprocessors.
One difficulty in dealing with a multiple processor array is that of handling interrupts between the System Bus and the array of processors. This is due to the fact that a device on the System Bus side of the global bus sends out an interrupt in a normal matter which must then be transmitted to one or more of the processors in the array to be serviced. This requires the global bus to be occupied for the interrupt period in order for anyone of the processors to, first, recognize the interrupt and, second, to then service the interrupt. This is difficult when dealing with multiple processors in that some scheme must be developed in order to define which of the processors is to service the interrupt. This can be difficult if an interrupt is to be serviced by more than one processor.
The present invention disclosed and claimed herein comprises interprocessor communication device for communicating between first and second processors. Each of the first and second processors has a communication protocol associated therewith for transmitting data thereto and receiving data therefrom. An interprocessor buffer is provided for storing data, the buffer having a first communication port and a second communication port for communicating therewith in a third buffer protocol. Data can be transmitted into one of the first or second ports for storage in the buffer and retrieved from the other of the first and second ports for access of data from the buffer. A first translator is operable to convert the communication protocol of the first processor to the buffer communication protocol, and is disposed between the first processor and the first port of the buffer for allowing the first processor to communicate with the first port of the buffer in the associated communication protocol of the first processor. A second translator is provided for converting the communication protocol of the second processor to the buffer communication protocol and is disposed between the second processor and the second port of the buffer for allowing the second communication processor to communicate with the second port of the buffer in the associated communication protocol of the second processor.
In another aspect of the present invention, the communication protocols of the first and second processors each comprises a memory access protocol for accessing a predetermined type of memory which has a predetermined access protocol. The first and second translators are operable to translate the memory access protocol associated with the first and second processors to the buffer communication protocol, such that communicating with the buffer by either of the first or second processors is effected by the first and second processors with the memory access protocol.
In a further aspect of the present invention, a notification device is provided for notifying the one of the first and second processors to which data is being transmitted through the interprocessor buffer, such that data designated therefore is stored in the interprocessor buffer. The interprocessor buffer stores the data until retrieved by the receiving one of the first and second processors.